A parallel multi-layer channel router on the HVH model

Abstract

With the advancement of the silicon technology multi-layered VLSI circuits and PCBs (printed circuit boards) have been widely used. Based on the neural network model this paper presents the first parallel algorithm for multi-layer channel routing problems on the HVH model which minimize wiring areas in VLSI circuits and PCBs. The algorithm requires n × m × 2 s processing elements for the n-net- m-track-3 s-layer problem. The algorithm not only runs on a sequential machine but also on a parallel machine with maximally n × m × 2 s processors. The algorithm is verified by solving seven benchmark problems where it finds better solutions than the existing algorithms for 6–12-layer problems in nearly constant time on a parallel machine.