Channel Routing Problems

Abstract

A parallel algorithm for channel routing problems is introduced in this Chapter. The channel routing problem is very important in automatic layout design of VLSI circuits and printed circuit boards. The problem is to route the given interconnections between two rows of terminals on a multi-layer channel where the channel area must be minimized. Although several algorithms have been reported for two-layer problems, two-layer-and-over-the-cell problems, and three-layer problems, the current advancement of the VLSI technology allows us to use four layers composed of two metal layers and two polysilicon layers for routing in a chip where no parallel algorithms have been proposed. The goal of the proposed parallel algorithm is to find a near-optimum routing solution for the given interconnections in a short time. The algorithm is used for the four-layer channel routing problem where it requires n×m×2 processing elements (neurons) for the n-net-m-track problem. The algorithm has three advantages over the conventional algorithms; 1) it can be easily modified for accommodating more than four-layer channel routing problems, 2) it runs not only on a sequential machine but also on a parallel machine with maximally n×m×2 processors, and 3) the program size is very small. The algorithm is tested by solving seven benchmark problems where the algorithm finds routing solutions in nearly constant time with n×m×2 processors. This Chapter is based on a paper published in IEEE Trans, on Computer-Aided Design (Funabiki and Takefuji 1991).