A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications

Abstract

Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.