A Novel Voltage-Mode Lut Using Clock Boosting Technique in Standard CMOS

Abstract

In a VLSI circuit, interconnection plays the dominant role in every part of the circuit nearly 70 percent of the area depends on interconnection, 20 percent of area depends on insulation, and remaining 10 percent to devices. The binary logic is limited due to interconnect which occupies large area on a VLSI chip. In this work, the designs of quaternaryvalued logic circuits have been explored over multi-valued logic due to the following reasoning. An approach to mitigate the impact of interconnections is to use multiple-valued logic (MVL), hence, more information can be carried in each wire, reducing the routing network. Therefore, a single wire carrying a signal with N logic levels can replace log N having base 2 wires carrying binary signals. Reducing the routing leads to a direct reduction of the line capacitance and the overall circuit area. Therefore, this results in increasing the maximum operation frequency and also reducing the power consumption. The most important characteristics of this method is a voltage-mode structure. Voltage mode structure has the advantages like reduced power consumption implemented in a standard CMOS technology. Our new method overcomes conventional techniques with simple and efficient CMOS structures.