A Novel VLSI Architecture of Multiplier on Radix 4 using Redundant Binary Technique

Abstract

The work mainly deals with in improving multiplication process by using Redundant Binary Technique. By implementing the existing method of Multiplication and Accumulation structure in Real time applications, occurs some difficulties like some hard multiples, and getting partial products in multiplication stage, it was not useful for higher radix values. The covalent redundant binary booth encoding algorithm overcomes the hard multiple generation problem and it reduces the partial products. The proposed algorithm dumped into the Booth encoding partial product generation stage. In this stage first step is to change the normal binary to redundant binary to make simple to avoid hard multiples. The partial products also reduce in the same stage. The method is implemented in the Fast Fourier Transform, Digital signal processors, and in Arithmetic logic unit. Finally the output results acquired for this method is number of gates are reduced and partial products are reduced up to 32 for 128 bit processor.