A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability

Abstract

This paper presents a novel low-power Tunneling Field-Effect-Transistor (TFET) 8T-SRAM cell. The proposed cell uses a supply feedback to improve its stability. The new structure at the supply voltage of 300 mV, compared to the conventional 6T SRAM, shows 33% and 26% improvements in Read Static Noise Margin (RSNM), and write margin (WM), respectively. Layout drawn in 32-nm technology shows that the proposed 8T cell offers 1.2X larger area overhead compared to the conventional 6T cell, however with considering of higher performance and stability of the proposed design at low supply voltages, this is worthy of use. Also, proposed design shows better performance under process variations compared to the 8T-SRAM cell designed using other technologies.