Abstract
Leakage power has become a serious concern in nanometer CMOS technologies. Dynamic and leakage power both are the main contributors to the total power consumption. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In this paper, a technique has been proposed which will reduce simultaneously both glitch and leakage power. The results are simulated in Microwind3.1 in 90nm and 250 nm technology at room temperature.
Highlights
The development of digital integrated circuits is challenged by higher power consumption
Dynamic and leakage power both are the main contributors to the total power consumption
Static power has been overshadowed by dynamic power consumption, but as transistor sizes continue to shrink, static power may overtake dynamic power consumption To alleviate the rising significance of static power in digital systems, static power reduction technique shave been developed like transistor stacking, dual threshold voltage, MTCMOS etc
Summary
M.E. Student, Department of Electronics and Communication Engineering NITTTR, Chandigarh, India. Associate Professor, Department of Electronics and Communication Engineering NITTTR, Chandigarh, India. Abstract—Leakage power has become a serious concern in nanometer CMOS technologies. Dynamic and leakage power both are the main contributors to the total power consumption. The dynamic power has dominated the total power dissipation of CMOS devices. With the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. A technique has been proposed which will reduce simultaneously both glitch and leakage power. The results are simulated in Microwind3.1 in 90nm and 250 nm technology at room temperature
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