Abstract
In floating gate flash memories, anode hot hole injection induced by the channel FN erase will result in tunnel oxide degradation, severe read disturbance and an abnormally fast program. All of these issues are critical for multilevel cell (MLC) flash memory design, which requires precise threshold voltage placement, good data retentivity and programming controllability. In this paper, a novel soft-program scheme is proposed to narrow the threshold voltage distribution in the first level. Cycling-induced read disturbance and programming inaccuracy are also reduced. This technique is essential for the application of more-than-2-bit MLC flash memories.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
