A novel sleepy stack 6-T SRAM cell design for reducing leakage power in submicron technologies

Abstract

Static power dissipation is a dominant field in deep sub-micron technologies. Technology scaling down into submicron technology to achieve higher operating speed of CMOS circuits, the leakage power becomes more and more. As process geometrics move to finer technologies, device consistency and threshold voltage becomes much smaller. When decreasing the supply voltage intends to its decreasing the threshold voltage and oxide thickness. Tremendous increasing in device density and reducing threshold voltage result it vigorously increases the leakage power. The main motivation of this article is to reduce leakage power and to maintain the logic state. We propose a new technique by combine of older technique in accordance with leakage power, critical path delay and feasibility issues. The proposed technique simulated in Tanner-SPICE using 180nm, 90nm and 45nm process technology and convincing power reduction is achieved with minimum critical path delay.