Abstract
The paper presents a comprehensive analysis of signal intermixing taking place across the injectors of frequency-divide-by-three circuits with divide-by-two secondary locking. The analytical results confirmed by circuit simulations provide an insightful understanding of the circuit operation, and inspire the design of a novel single-inductor injection-locked frequency divider (ILFD) by three, where injection is reinforced by a dual-injection scheme with no penalty in power dissipation. The novel circuit, when benchmarked against existing ILFD topologies, optimized in a 65-nm LP CMOS process, shows about a three-time larger locking range with respect to the single-inductor divider by three with a floating-source injector, and about a 40% improvement with respect to the single-inductor divider by three with divide-by-two locking, for the same power dissipation. The novel topology has been adopted in a 15-GHz divider by three for a 5G radio-frequency synthesizer, reaching a 23.6% locking range at 1.56-mW dc power, featuring one of the best performances among divide-by-three ILFDs and a compact size of only 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems I: Regular Papers
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
