A novel self-checking carry lookahead adder with multiple error detection/correction

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Evolving processing units in complex computing systems are dealing with smaller gates and devices which are seriously influenced by external effects such as electromagnetic noises and single event transient (SET) effects. Due to this increasing sensitivity, several transient faults might appear at the same time in a processing unit which can lead to multiple simultaneous errors. In this paper, a novel carry lookahead adder design is presented with multiple error detection/correction capability. The proposed self-checking architecture utilizes a modified parity prediction scheme combined with a partial triple modular redundancy distributed in all of the bit slices. This scheme fits carry lookahead adder and its arithmetic logic unit (ALU) counterpart in which the carry logic occupies a large part of the circuit. Furthermore, two alternative methods are proposed to reduce the overall hardware cost in the main proposed adder. The efficiency of the proposed architecture in multiple error detection/correction is analytically shown by probabilistic assessments and verified by simulations. However, the hardware implementation reveals that this architecture incurs much lower hardware overheads relative to traditional architectures while it provides higher error detection/correction efficiency.