A novel self-aligned gate process for half-micrometer gate GaAs ICs using ECR-CVD

Abstract

A substitutional self-aligned gate MESFET process for the half-micrometer gate GaAs IC that employs techniques of sidewall formation and precise pattern reversal using ECR (electron cyclotron resonance) CVD (chemical vapor deposition) is discussed. A FET with 0.45- mu m gate length showed high performance characteristics, such as a maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz. This process has two advantages over conventional substitutional and refractory gate processes. First, it can incorporate an LDD (lightly doped drain) structure. Second, since the photoresist dummy gates are precisely reversed without using reactive ion etching (RIE) at all, the gate length is dependent only on lithography. The process was demonstrated by the preliminary fabrication of a 16 b*16 b multiplier with 50% yield. The process, with high-performance device characteristics, should fine broad applications in both half-micrometer gate level LSIs and analog ICs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>