Abstract
Partial sorting, selecting M largest/smallest numbers from N inputs, is of interest in many applications. Thus, this brief presents a novel scheme for real-time max/min-set-selection sorters on field-programmable gate arrays (FPGAs). Our scheme has good expansibility but no close relation with the vector length, whose basic idea is reducing the programming complexity through the essence of sorting networks for Bitonic sequences. In addition, two modified forms of our scheme are proposed to solve the high data rate sequence and a multiple of 2 max/min-set-selection problem respectively. Finally, the effectiveness of our scheme is demonstrated on one Xilinx XC7VX690T FPGA by performing comparisons with state-of-the-arts.
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