Abstract
We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.
Highlights
: We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs)
A feedback path including an operational amplifier (OPA) is introduced to keep the difference between the charge pump output voltage VDDOD and the VCSEL forward voltage to be constant at ΔV = I1R2
This paper describes the design and the performance of a 4×10 Gbps VCSEL array driver, cpVLAD, which is fabricated in a 65 nm CMOS process
Summary
To reduce the Inter-symbol interference (ISI) jitter, the LA is designed to provide enough gain with high bandwidth. Considering the minimum input amplitude of 100 mV, the total gain of the LA is designed to be greater than 18 dB with a total bandwidth larger than 10 GHz. The LA has four fully differential amplification stages [13] with an inductive shunt-peaking technique [14] to boost the bandwidth. To fully take advantage of the on-chip inductor, we have two consecutive stages sharing one inductor [15]. The schematic of two consecutive stages with a shared inductor is shown in figure 2. The overall gain of the LA is 21.5 dB, and the bandwidth is 12.0 GHz
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