Abstract
The behavioral model of previously proposed novel sync cell and pulse synchron¬iz¬er design is presented․The behavioral model is developed using Verilog HDL. Pulse synchro¬n¬izer designed is based on the sync cell model and verified with X-injection duri¬n¬g the simulations to identify failures in early design stages. The use of the designed synchronizers reduces overall area and the clock cycle required for synchronization whi¬c¬h improves the performance of the overall system where they are used.
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