A novel processing structure to reduce computational delay in high-performance digital controllers

Abstract

With the development of VLIC technology, the use of digital controllers has dramatically increased in modern industrial applications. However an inevitable consequence is the presence of computational delay; defined as the time lag between the input and output instructions in the processor, in satisfactorily completing the control algorithm. Although great advantages exist in the use of digital controllers, it has been found that computational delay can be a significant problem for fast systems, e.g. electrical drives, robots, etc. There are three approaches to dealing with computational delay in designing a digital controller for a particular plant: ignore computational delay; recognise, but simply accept computational delay; and reduce computational, delay. Based on control theory for time delay systems, the paper proposes a software approach which can reduce computational delay beyond that achieved by traditional numerical optimisation.