Abstract
A high-performance CMOS technology and cell structure for a megabit EEPROM are described. A novel EEPROM (electrically erasable programmable read-only memory) cell called a stacked floating gate with self-aligned tunnel region (SSTR) cell has been developed. A merged signal transistor structure has been developed to reduce the cell size. A sufficient cell threshold window is obtained in 2 ms at 16 V in both write and erase operation, using Fowler-Nordheim electron tunneling between the floating gate and the n/sup +/ region. The endurance of the cell is greater than 100000 erase/write cycles. An SSTR cell with a capacitive coupling ratio of 0.83 and a cell area of 30.4 mu m/sup 2/ has been implemented in a 1-Mb EEPROM. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
