A novel precision MOS synchronous delay line

Abstract

Unlike common delay lines, which are implemented in hybrid technologies, the SDL is implemented in MOS. Thus the SDL obviates the need in certain applications for separate delay-line components, since it can be integrated directly into LSI or VLSI components implemented in common MOS technologies. The SDL was implemented for the first time in a commercial DRAM controller, in which it provided precision trigger pulses for the DRAM control signals. The SDL utilizes the system clock as a delay reference. The negative feedback that is intrinsic to the SDL design also makes it very insensitive to supply-voltage, temperature, and processing variations. A delay analysis predicts a linear relationship between the delays provided by the taps and the input reference clock. This linear relationship was confirmed experimentally, as was the low sensitivity of the SDL to temperature and voltage-supply variations. A closed-loop analysis defines the circuit parameters that determine stable and optimum operation.