Abstract
Template matching based on zero-mean normalized cross-correlation measure (ZNCC) has been widely used in a broad range of image processing applications. To meet the requirements for high processing speed, small size, and variable image size in automatic target recognition systems, a novel field-programmable gate array (FPGA)-based parallel architecture is presented in this paper for the ZNCC computation. The proposed architecture employs two groups of RAM blocks, one of which is used for the multiply-accumulate operations of the real and the reference images and the other for data rearrangement of the reference image, and their functions are switched through 2-input multiplexers when searching at the next row. Moreover, the sum of the pixels in the searching area of the real image is computed through serially accumulating the differences between the new column in the current searching area and the old column in the last searching area using one dual-port RAM. Simultaneously, the sum of the squares of the pixels is calculated in the same way. Using the Altera Stratix II FPGA chip (EP2S90F780I4) as the target device, the compilation results with Quartus II show that compared with the traditional architecture, the synthesis logic utilization decreases from 63% to 35% and the usage of DSP blocks decreases from 59% to 39%, while the memory bits only increase by 8% and the usage of other resources is nearly the same. The simulation and practical experimental results show that the proposed architecture can effectively improve the performance of the practical automatic target recognition system.
Highlights
Template matching has been widely used in a broad range of applications related to computer vision and image processing, such as automatic target recognition, medical image fusion for diagnosis [1], satellite image monitoring, and binocular stereo vision [2], etc
Using the Altera Stratix II field-programmable gate array (FPGA) chip (EP2S90F780I4) [16] as the target device in an automatic target recognition system with a reference image with maximum size of 80 × 80 and a real-time image with maximum size of 512 × 512, the compilation results with Quartus II 8.0 [17] have shown that, compared with the traditional architecture, the usage of ALUTs of the proposed architecture decreases from 46% to 19%, the usage of DSP blocks decreases from 59% to 39%, and the logic utilization decreases from 63% to 35%, while the memory bits only increase by 8% and the usage of other resources is nearly the same
During the ABcc computation at this searching row, the reference image is input to ORAMA according to the sequence of RAM blocks of the real image (RRAM) used for computing at the third row of the real image, as shown in Fig. 4 (b)
Summary
Template matching has been widely used in a broad range of applications related to computer vision and image processing, such as automatic target recognition, medical image fusion for diagnosis [1], satellite image monitoring, and binocular stereo vision [2], etc. To meet the requirements for high processing speed, small size, and variable image size in an automatic target recognition (ATR) system, a novel FPGA-based parallel architecture is proposed to further reduce the resource utilization and processing time of the ZNCC computation with a variable image size in this paper. Using the Altera Stratix II FPGA chip (EP2S90F780I4) [16] as the target device in an automatic target recognition system with a reference image with maximum size of 80 × 80 and a real-time image with maximum size of 512 × 512, the compilation results with Quartus II 8.0 [17] have shown that, compared with the traditional architecture, the usage of ALUTs (adaptive look-up tables) of the proposed architecture decreases from 46% to 19%, the usage of DSP blocks decreases from 59% to 39%, and the logic utilization decreases from 63% to 35%, while the memory bits only increase by 8% and the usage of other resources is nearly the same. The ABcc(u,v) term in the numerator of (2) denotes the standard cross-correlation between the template and the portion of the real image under examination, i.e., the standard cross-correlation operation is contained in the ZNCC computation
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