A Novel Output-capacitorless Low-Dropout Regulator for Power Management

Abstract

A novel output-capacitorless low-dropout regulator (OCL-LDO) for power management is implemented in 130nm CMOS technology. The structure of the LDO is based on a flipped voltage follower (FVF), while the control voltage generation loop and the error amplifying loop are combined to achieve higher gain and bandwidth, without increasing quiescent current. In addition,the output voltage serves to reduce the voltage variation caused by device mismatch.The proposed LDO is compensated by a single Miller capacitor to maintain the closed-loop stability with load capacity of 100mA. The line regulation and the load regulation could be improved to less than 5mV/V and 0.1mV/mA. A voltage spike repression unit is designed for the improvement of slew rate and transient performance. When the load current varies from 3mA to 100mA within 100-ns edge time, the maximum overshoot is less than 150mV with the supply voltage from 1.2V to 1.4V, and the recovery time less than 5µs.