A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC

Abstract

In this paper, a novel on-chip impedance calibration methodology for a LPDDR4 (low power double data rate) application is proposed. The background calibration operates to compensate mismatches and variations of the output NMOS drivers from process and temperature variations. The impedance matching concept uses process sensor and temperature monitoring sensors closely located to DQ pins as a means to detect output driver transistor mismatches due to process and temperature variations. In addition, digitized sensor outputs from ADCs are used as inputs of look-up tables, which control calibration codes of the transmitter driver. The proposed circuitry is designed with DRAM bidirectional transceiver and implemented using a standard 180nm CMOS technology, and the impedance calibration technique is demonstrated with external termination resistance of 40/48/60/80/120/240 ohm, respectively. In the receiver end, a PMOS input sense amplifier is designed considering the required common mode range for the LVSTL (low voltage swing termination logic) signal interface, and an adaptive gain control scheme is also applied on the receiver design. The process sensor is utilized to control the gain factor of the receiver. The active area including power-ring of the transmitter is 14.4mm2 with only 0.48mm2 of the proposed calibration circuit overhead.