A novel methodology for transistor-level power estimation

Abstract

Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In this papel; we introduce cc1 method which extends the Monte-Carlo approach for deriving the average power dissipation of a circuit using transistor-level power simulators. To reduce the simulation time, we propose a mixedlevel extrapolation technique to speed up the convergence rate of the process, and thereby to achieve a good balance between simulation time and accuracy. Experimental results show that this is a promising method for deriving the accurate power dissipation of a circuit within reasonable time budget. 1. Introdiuction For a CIMOS circuit, the power dissipation is primarily caused by three types of currents: device leakage current, short-circuit current, and dynamic transition current. It is known that the power dissipation caused by device leakage current (staric current) is usually very small and negligible as compared with the dynamic transition current. The shortcircuit curre:nt occurs whenever a path from v,d to ground is conducted at a device for a short period of time. In some cases, shon:-circuit current cannot be ignored. However, only the trimistor-level simulators with continuous-time modeling of the device can accurately take this part into