A novel method of hotspot temperature reduction for a 3D stacked CMOS IC chip device fabricated on an ultrathin substrate

Abstract

A high-performance thermal management method for three-dimensional integrated circuit (IC) integration has been developed for use in conjunction with a three-dimensional (3D) large-scale integration (LSI) technology. By depositing a 10 µm thick high thermal conductivity (HTC) film consisting of 1680 alternating layers of silicon and graphite nano-films directly onto the backside of a Si substrate via an automatic sequencing sputtering method, reduction in the transient hotspot temperature in a thin-substrate CMOS IC chip is achieved. It is shown that this novel HTC film is able to overcome the thermal problems associated with thin substrates and allow the cooling of stacked ICs. In the work described in this paper, we demonstrated the performance of the HTC using a 100 µm thick substrate IC chip consisting of a complementary metal-oxide semiconductor (CMOS) ring oscillator circuit film. Our experimental results, which were confirmed in simulation, reveal a 28% reduction in the hotspot temperature rise owing to the presence of the HTC film. This technology is applicable to future developments in the 3D ultrathin substrate LSI chip stacking technology utilizing through-silicon vias (TSVs) and micro-bumps.