Abstract
A novel technique for selective NPN transistor storage time control on a silicon monolithic, integrated chip is described. The method exploits the parasitic PNP transistor which is inherent in the basic diffused isolation structure of epitaxial integrated circuits. This unique four-layer NPNP structure permits the excess stored charge in the collector of a saturated NPN transistor to be shunted to the substrate by the action of the parasitic PNP. The switching performance of devices fabricated in this manner are superior to any saturating transistors now available with little compromise in saturation voltage. Storage times of less than one nanosecond are achieved on a reproducible basis. An analysis of the operation of the device is presented, including the theoretical and empirical relationship between the f T of the PNP and the storage time of the saturating NPN.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call