A novel low-power FPGA routing switch

Abstract

We propose a new programmable FPGA routing switch that can operate in three different modes: high-speed, low-power or sleep. High-speed mode offers similar power and performance to a traditional routing switch. In low-power mode, power is reduced at the expense of speed. Leakage power is reduced by 36-40% in low-power vs. high-speed mode (on average); dynamic power is reduced by up to 28%. Leakage power in sleep mode is 61% lower than in high-speed mode. The applicability of the new switch is motivated through an analysis of timing slack in industrial FPGA designs. Specifically, we show that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.