A Novel Low Leakage Power FPGAs Look-Up Table

Abstract

This paper proposed a novel low leakage FPGAs look-up table (LUT) that can operate in three different modes: high-speed, low-power or sleep. In high-speed mode, the LUT provide similar power and performance to a conventional LUT. In low-power mode, as the expense of speed, leakage power is reduced by 68%~73% vs. high-speed mode. Leakage power in sleep mode is over 95% lower than in high-speed mode