A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter

Abstract

In this paper, a new low power and variable resolution flash ADC is proposed. Comparators of conventional flash ADC are replaced with CMOS inverters whose threshold can be varied dynamically. A novel peak-detector circuit is employed to achieve variable resolution as well as to switch the unused parallel inverters to standby mode. Linear reduction in resolution leads to exponential reduction in power. The ADC is capable of operating at 4-bit, 6-bit, and 8-bit precision and at a supply voltage of 2.5 V, it consumes 21.5 mW at 8-bit, 9 mW at 6-bit and 3.5 mW at 4-bit resolution. The sampling frequency ranges from 0.8 to 1.6 GSPS, and the ADC has a DNL < ±0.4 LSB, INL < ±0.36 LSB, SNR of 47 dB and SNDR of 46.3 dB for 8-bit operation. The proposed 'inverter-based' flash ADC operating at 8-bit precision and conventional 8-bit comparator-based flash ADC have been designed, compared and verified for post layout simulations in standard 65 nm CMOS technology.