A Novel Low Dynamic Resistance Dual-Directional SCR with High Holding Voltage for 12 V Applications

Kyoung-Il Do,Yong-Seo Koo

doi:10.1109/jeds.2020.2999108

Abstract

The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-voltage and high-voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low holding voltage of existing DDSCRs is not suitable for high-voltage applications. In this study, a novel DDSCR with a high holding voltage and low dynamic resistance is proposed and its electrical characteristics are verified. The proposed DDSCR has two additional internal parasitic bipolar transistors compared to a conventional low- triggering voltage DDSCR (LTDDSCR). Self-gate biasing reduces latch-mode feedback between the parasitic bipolar transistors in the SCR. The device is fabricated using 0.13 $\mu {\mathrm{ m}}$ BCD processes and implements a segment layout resulting in a very low dynamic resistance of $2.2~{\Omega }$ and excellent holding voltages of up to 17.2 V. The proposed DDSCR demonstrates improved reliability and area efficiency for 12 V applications.

Highlights

The proposed device, on the other hand, operates within the 12V-class ESD design window with a trigger voltage (Vt1) of 18.7V and a holding voltage of 13.6V. This behavior occurs because the SCR feedback is attenuated by the βpnp reduction of the parasitic bipolar transistors (Qp2, Qp3) which form the serial bus of the low-dynamic -resistance-dual SCR (LDRDSCR)
The proposed device has enhanced electrical characteristics from two additional parasitic bipolar transistors which operate according to the ESD polarity
The gate bias using the potential rise of the P region maintains excellent dynamic resistance (2.2 ) while increasing the carrier concentration of the base region of the parasitic bipolar transistors, thereby improving the holding voltage (13.6 V)

Summary

Introduction

SCRs are controlled by parasitic NPN and PNP bipolar transistors and have excellent ESD robustness and clamping capability per unit area. By providing an additional ESD discharge path, the recently proposed low-dynamic -resistance-dual SCR (LDRDSCR) [5] has an excellent dynamic resistance. The LTDDSCR inserts a P+ bridge in the middle of the structure to lower the avalanche breakdown voltage level, while the LDRDSCR has an excellent dynamic resistance due to the operation of additional PNP parasitic bipolar transistors.

Results

Conclusion