A novel lift-off process using low-temperature PECVD silicon nitride for the fabrication of self-aligned gate GaAs MESFETs and InP MISFETs

Abstract

A novel lift-off process for the fabrication of self-aligned gate GaAs MESFETs and InP MISFETs was developed using low-temperature plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films. The gate areas of the GaAs MESFETs and InP MISFETs were defined by silicon nitride lift-off in a substitutional gate process so that the gate electrodes of the field effect transistors were automatically aligned with the source and drain areas. The lift-off of silicon nitride was made possible by characterizing PECVD silicon nitride at low temperatures and performing the silicon nitride deposition at 60°C which was lower than the soft bake temperature of normal photoresist.