Abstract
A novel layout has been proposed to reduce the single event upset (SEU) vulnerability of SRAM cells. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors. For the angle incidence, the proposed layout is immune from ion hit in two plans, and is more robust against SEU in other two plans than the conventional one. The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%. Consequently, the layout strategy proposed can gain both reliability and area cost benefit simultaneously.
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