Comparing Single Event Upset sensitivity of bulk vs. SOI based FinFET SRAM cells using TCAD simulations

Abstract

Single Event Upsets (SEUs), or soft errors, in SRAMs are changes of logic state due to an energetic particle depositing energy on a sensitive node within the cell. FinFETs continue to receive much attention as a next-generation silicon CMOS device structure, and have been demonstrated on bulk and SOI substrates. The small dimensions and operating voltages of these devices can make them suceptible to SEU. Here, we compare the relative SEU sensitivity of bulk and SOI FinFET SRAM cells using technology computer aided design (TCAD) simulatons. While the critical charges are comparable for the two embodiments, the larger collection volume of the bulk cell may result in upsets for lower linear energy transfer (LET) particles, as well as a larger sensitive area (SEU cross section).