A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory

Abstract

Delay units play an important role in bitline design for on-chip memory. Traditional delay units can be categorized into two types: passive ones and active ones. In this paper, a novel hybrid delay unit (combination of passive and active ones) using dummy through-silicon vias (TSVs) in 3-D on-chip memory is proposed for modern microprocessors. Dummy TSV delay units (DTDUs) are developed in multilevel bitlines of a 128-kB 3-D on-chip memory with 180- and 45-nm CMOS technologies. Experimental results show that DTDUs, with negligible power overhead, have higher immunity to supply voltage and process variations while taking less silicon area and enhancing heat dissipation, compared to traditional delay units.