A novel fault injection method for system verification based on FPGA boundary scan architecture

Abstract

A novel fault injection (a.k.a. fault insertion) method to facilitate the development of high quality system test is presented in this paper In this method, we utilize the existing boundary scan (BS) architecture of an FPGA to inject a hardware fault condition at any pin of the FPGA on a circuit board. Existing user-defined instructions of most FPGA BS architectures and the newly proposed design of their corresponding user-defined scan registers (USRs) constitute the proposed fault injection architecture. No new instruction, and no modification of the existing test access port (TAP) controller and BS registers are required. In addition, it is possible to reconfigure where and what type of faults to be injected asynchronously via the BS architecture while the system is online. Although the proposed method incurs at least additional delay through a multiplexer on the pin where a fault is injected, the programmability of an FPGA enables us to add fault injection logic only to where fault injection function is desired. Hence, area overhead and performance impact can be significantly reduced.