Abstract
In this paper, dimensional coding of projection has been developed with the hardware design for RS algorithms. The result of simulation of Memory Interface Unit for basic and dimensional projection coding with scale and Implemented Video Interface module using VHDL and Target on to the FPGA implemented (XCV300-bg432-6). It provided operating speed of 732.5 MHz, power consumption of 1249 BEL and 128.3 mW in FPGA.
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