Abstract
In this brief, a novel digital duty-cycle modulation (DDCM) scheme is outlined. The digital part, embedded in a field-programmable gate array (FPGA) chip, consists of a lookup DDCM map, a dual DDCM counting logic with interrupt service routines, and a holder. It is used as a building core of a well-tested 10–12 bits FPGA-based digital-to-analog converter (DAC). Experimental tests show that for a digital input bandwidth of 3 kHZ, the new DDDM technique for DAC achieves 40 dBc of surpious free dynamic range and 60 dB of NOISE FLOOR range. This performance is a challenge compared with most low cost oversampling DACs schemes with single decimation stage.
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