A novel digital calibration technique for gain and offset mismatch in parallel TIΣΔ ADCs

Abstract

Time interleaved sigma-delta architecture is a potential candidate for high bandwidth analog to digital converters required for reconfigurable, versatile and multistandard receivers. However, this architecture is very sensitive to the unavoidable gain and offset mismatch resulting from the manufacturing process. This paper presents a novel digital calibration method for gain and offset mismatch. This new method takes advantage of the digital signal processing on each channel to reconstruct the useful signal and requires only few logic components for implementation. The run time calibration is estimated to 10 and 15 clock cycles for offset and gain mismatches respectively.