A Novel Design Approach of Low Power Consuming Decoder using Reversible Logic Gates

Abstract

In current scenario, the reversible logic design is attracting more interest due to its low power consumption. Reversible logic is very important in low-power circuit design. The important reversible gates used for reversible logic synthesis are Feynman Gate, Fredkin gate, toffoli gate, new gate and peres gate etc. Reversible Logic requires non-destruction of information. Therefore the number of inputs must be equal to the number of outputs. (If there were more outputs than inputs, the reverse direction wouldn't be reversible!). This paper presents a compact realization of quantum n-to-2n decoder circuit, where n is the number of input bits. The proposed design of the decoder circuit shows that it is composed of the quantum 2-to-4 decoder circuit. We present a decoder circuit using simple Feynman gate and tofolli gates. Designed circuit performs better than the existing ones, e.g., the proposed decoder circuit improves on the number of gates, delay, area and power. We simulated the circuit using cadence tool in both analog and digital.