Design and Implementation of Power Optimal Reversable Fir Filter using Wallace Tree Multiplier

Abstract

In present development, the reversible logic design fascinating more attention due to its low power consumption. Reversible logic is very significant in low-power circuit design. The imperative reversible gates used for reversible logic synthesis are Feynman Gate, Fredkin gate, Toffoli gate, and peres gate etc. In this paper, an efficient architecture of FIR filter structure is presented. For achieving low power, reversible logic mode of operation is implemented in the design. It also gives brief idea to build adder circuits using the basic reversible gate like peres gate and TSG gate.