A novel conflict-free parallel memory access scheme for FFT constant geometry architectures

Abstract

In this paper, a parallel conflict-free access scheme for a constant geometry architecture which is unlike the previous schemes is proposed. The proposed method only uses one modular addition operation, and does not involve complicated operations, thus reducing the hardware complexity of address generation. Because of the reduction of the combinational logic which is used to generate the access address, the scheme also reduces the time delay and accordingly improves the executable frequency of fast Fourier transform (FFT) processors. In the scheme, we use an arbitrary radix, i.e., radix-r, to implement the scheme. The scheme is not only applicable to radix-r FFT processors with one butterfly unit, but is also suitable for FFT processors with multiple butterfly units. Because the same architecture is used for every stage of the constant geometry, it can enhance the flexibility of the FFT implementation. Finally, we analyze the resource costs and time delay of the proposed method, and the results verify the advantages of the proposed scheme.