A novel CBi-CMOS technology by DIIP process

Abstract

To realize high performance mixed analog and digital ASICs, a novel CBi-CMOS technology is proposed. This technology, called DIIP (double-implanted and isolated P-well) CBi-CMOS technology, is characterized by a structure with vertical NPN, PNP and CMOS structures on the same chip. In this structure, a vertical PNP transistor and NMOS transistor are fabricated in a P-well, which is isolated from the P-type substrate by the N+ buried layer and has a deep P+ region created by high-energy ion implantation. This deep P+ region acts as a subcollector for the vertical PNP transistor and as a punch-through barrier from the N+ source/drain of the NMOS transistor to the N+ buried layer. Since the P-well is separated from the substrate, a dual power supply can be used for linear circuits