Abstract

Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable Network-on-Chip (NoC) systems with high communication performance. In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms in NoCs. The common idea of the fault-tolerant routing has been undoubtedly to detour faulty nodes, while our approach allows passing through faulty nodes with the slight modification of NoC architecture. As a design example, we present an XY-based routing algorithm with the passage function. To investigate the effect of the approach, we compare the communication performance (i.e. average latency) of the XY-based algorithm with well-known region-based algorithms under the condition of with and without virtual channels. Finally, we provide possible directions of future research on the fault-tolerant routing with the passage function.

Highlights

  • Demand for computation power will never stop, and it is ever increasing year by year in a variety of scientific research fields

  • Motivated by the problem presented in the previous section, we introduce a novel approach based on the opposite idea of the common approach; our approach allows packets to pass through the faulty nodes with slight modification of NoC architecture

  • We have introduced a novel approach for the design of fault-tolerant routing algorithms in 2D mesh NoCs

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Summary

Introduction

Demand for computation power will never stop, and it is ever increasing year by year in a variety of scientific research fields. Designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable NoC systems with high communication performance. There exist several basic approaches, as we reviewed, the common idea of the fault-tolerant routing remains unchanged from the earliest, and it has been undoubtedly to detour faulty nodes. It is obvious that detouring faulty nodes increases the communication latency as the packet is misrouted apart from the minimal path to the destination. The rest of this chapter is organized as follows: Section 2 presents the architecture of NoC, the basis of packet routing, and the related works of fault-tolerant routing algorithms.

NoC architecture and fault-tolerant routing
A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs
Deadlock
Related works
Basic approach and NoC architecture
Design methodology for fault-tolerant routing algorithms
Routing algorithm based on XY routing
Evaluation condition
Overall trend
Performance comparison of routing algorithms with increased VCs
Performance comparison of routing algorithms with fixed number of VCs
Circuit amount
Conclusion and future work

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