Generation and Performance Evaluation of Reconfigurable Fault Tolerant Routing Algorithm for 2D-Mesh NoC

Abstract

Abstract Recent design techniques are integrating 10 to 100 embedded functional and storage blocks in a single system on chip and the number is growing to increase with further advancements. The bus based interconnections are not a suitable alternative for Massively Parallel Multi-Processors Systems on Chip (MPSoCs) because of power and latency issue. The communication requirements of many-core embedded systems are addressed by the Networks on Chip (NoC) paradigm. In this paper, a minimal and fault tolerant routing algorithm is proposed so as to route packets adaptively through the shortest path in the presence of faulty nodes. Using fault-tolerant routing algorithm to reroute packets around faulty nodes will increase latency. Besides, the performance of NoC is heavily affected by network congestion. Congestion in the network increases the time to traverse a packet from a source to a destination. The proposed routing algorithm adaptively chooses the next node where to send packet, so as to avoid packet drop in presence of congestion. The algorithm does handle both single and multiple busy nodes using reconfigurable paths (minimal and/or non-minimal).