A Novel and Efficient Hardware Accelerator Architecture for Signal Normalization

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Normalization and envelope generation of signals are essential pre-processing steps in many signal processing applications. With the emergence of high-performance computing and the need for hardware accelerators in digital signal processing, research for hardware efficient solutions has become a necessity. Interpolation and signal normalization algorithms, though have been implemented in software systems extensively, however, lack the research in hardware system solutions. In this paper, an envelope-based signal normalization technique has been presented along with a detailed discussion on the usage of cubic hermite interpolation. The hardware accelerator architecture for cubic hermite interpolation is presented, and the same is implemented on a field-programmable gate array (FPGA). It is found that the envelope method of normalization which uses interpolation performs better in terms of speed, hardware re-usability and complexity. Using cubic hermite interpolation, an architecture for hardware accelerator for the signal normalization is implemented on FPGA. The hardware accelerator is tested using data obtained from frequency-modulated continuous wave radar. The MATLAB simulation results for both interpolation and normalization are compared with the FPGA implementation results of the same. An average root mean square error and correlation of $$1.67 \times 10^{-4}$$ and 99.78% for interpolation and $$2.1 \times 10^{-4}$$ and 99.71% for normalization are obtained.