A novel algorithm combining oversampling and digital lock-in amplifier of high speed and precision

Abstract

Because of a large amount of arithmetic in the standard digital lock-in detection, a high performance processor is needed to implement the algorithm in real time. This paper presents a novel algorithm that integrates oversampling and high-speed lock-in detection. The algorithm sets the sampling frequency as a whole-number multiple of four of the input signal frequency, and then uses the common downsampling technology to lower the sampling frequency to four times of the input signal frequency. It could effectively remove the noise interference and improve the detection accuracy. After that the phase sensitive detector is implemented. It simply does the addition and subtraction on four points in the period of same phase and replaces almost all the multiplication operations to speed up digital lock-in detection calculation substantially. Furthermore, the correction factor is introduced to improve the calculation accuracy of the amplitude, and an error caused by the algorithm in theory can be eliminated completely. The results of the simulation and actual experiments show that the novel algorithm combining digital lock-in detection and oversampling not only has the high precision, but also has the unprecedented speed. In our work, the new algorithm is suitable for the real-time weak signal detection in the general microprocessor not just digital signal processor.