A Novel 4H-SiC JBS-Integrated MOSFET With Self-Pinching Structure for Improved Short-Circuit Capability

Abstract

Monolithic integration of junction barrier-controlled Schottky (JBS) diode with SiC MOSFET (termed JMOS) offers unique advantages. However, the short-circuit (SC) ruggedness issue stands in the way of the development of the conventional JMOS. The purpose of this numerical study is to investigate a new 4H-SiC JMOS with a self-pinching (SP) structure formed in the JFET region (termed SP-JMOS). The SP structure features that an N-type current spread layer is sandwiched between the P+ layer and the buried P-shield layer, forming a lateral JFET channel. In the forward conduction state, the lateral JFET channel self-pinches off and clamps the potential, thus limiting the saturation current of the device. In the blocking state, both the P+ layer and the buried P-shield layer collaboratively shield the Schottky contact and the SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface from a high electric field for long-term reliable operation. Numerical simulation results show that the proposed SP-JMOS not only withstands a roughly <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6\times $ </tex-math></inline-formula> longer SC withstanding time than that of the conventional JMOS, but also shows an ultralow oxide electric field in the SP-JMOS.