Abstract
A novel CMOS high speed divide-by-two circuit with very low power consumption is proposed in this paper. The circuit features very low input capacitance and a wide locking range of 1.5-18 GHz with a power consumption of less than 1.3 mW at 1.8 V. The input sensitivity of the stage is improved significantly when compared to conventional dynamic loaded high frequency dividers. The concept and design issue of the circuit is presented together with a performance comparison to existing topologies. The idea is demonstrated and verified in a standard 0.18 /spl mu/m CMOS process through realistic simulations originating from a complete layout using moderately extracted parasitics.
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