A 1.31mW 38GHz frequency divider in 90 nm CMOS technology

Abstract

In this paper, a high speed broadband divide-by-2 frequency divider is presented. The proposed divider is mainly a source-coupled logic (SCL) structure formed with two dynamic-loading master-slave D latches, which enables high frequency operation, low power consumption and high input sensitivity. This divider exhibits wide locking range from 8GHz∼38GHz and dissipates 1.31mW@38GHz from a 1.2V supply. The input sensitivity is only 4mV@16GHz. This chip occupies 685µm×430µm area with two on-chip spiral inductors in IBM 90nm CMOS process.