Abstract
A novel shallow trench isolation technology has been proposed for 0.25 /spl mu/m CMOS VLSI applications. The gate oxide and a thin poly layer are processed first, followed by the shallow trench isolation, channel implants, and high-energy well. The anomalous subthreshold conduction of the shallow trench isolated MOSFETs, as so called kink due to field crowding at active edge, has been successfully eliminated. No inverse narrow width effect is observed. The inter-well isolation, N/sup +//P/sup +/ spacing, is shrinkable down to 0.8 /spl mu/m for 0.25 /spl mu/m CMOS technology. Well behaved 0.25 /spl mu/m MOSFET's with off-state leakage less than 1 pA//spl mu/m, were obtained at 2.5 V supply voltage. This isolation technology has also been integrated into 0.25 /spl mu/m high-performance logic and high-density SRAM circuits.
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