A note on designing two-level carry-skip adders

Abstract

The worst-case carry propagation delays in carry-skip adders depend on how the full adders are grouped together (into blocks). We report an algorithm to configure 2-level carry-skip adders. The worst-case carry propagation delay of the carry-skip adder configurations determined by our algorithm are consistently *less* than the ones currently reported in the literature. Previous methods are applicable only to constant skip delay models and either do not guarantee an optimal configuration or suffered from a potentially exponential worst-case time complexity.