A non-zero delay model for glitch analysis in logic circuits

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One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows one to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we extend the concept of G-vector to support a non-zero delay model, which enables G-vector to be practically very efficient. A set of experimental results is provided to show the effectiveness of the proposed solution.